Design and development of low power NoC architecture using clock gating technique for SoC applications

Abstract The rise in scaling of integrated circuits has covered the design of complex System-on-Chip (SoC) systems, where hundreds of millions of transistors are combined on a single die. These systems are also exploited by modern technologies, such as telephone and automotive systems, to their benefit but with accompanying increases in power demand. This research paper proposes new architectural approaches to greatly reduce system power without sacrificing computing capability. This paper focuses on intelligent clock gating techniques to enhance SoC design power efficiency with Advanced eXtensible Interface (AXI) Interconnect based Network on Chip (NoC) architecture. The proposed architecture utilizes the data handling capabilities of AXI and scalability features of NoC, which collectively results in an impressive reduction in power consumption. The implementation results of intelligent clock gating in a Zynq ZCU104 SoC device demonstrate that the dynamic power consumption decreased from 1.568 W to 1.149 W, and static power decreased from 0.146W. In total, this has reduced the on-chip power from 1.714 W to 1.284 W, which is a significant improvement of 25.1%.