Parallelization is All System Identification Needs: End-to-End Vibration Diagnostics on a Multicore RISC-V Edge Device

The early detection of structural malfunctions requires the installation of real-time monitoring systems ensuring continuous access to the damage-sensitive information; nevertheless, it can generate bottlenecks in terms of bandwidth and storage. Deploying data reduction techniques at the edge is recognized as a proficient solution to reduce the systemfs network traffic. However, the most effective solutions currently employed for the purpose are typically based on memory and power-hungry algorithms, making their embedding on resourceconstrained devices very challenging; this is the case of vibration data reduction based on System Identification (SysId) models. This paper presents PARSY-VDD, a fully optimized PArallel end-to-end software framework based on SYstem identification for Vibration-based Damage Detection, as a suitable solution to perform damage detection at the edge in a time and energyefficient manner, avoiding streaming raw data to the cloud. First, we evaluate the damage detection capabilities of PARSYVDD with two benchmarks: a bridge and a wind turbine blade, showcasing the robustness of the end-to-end approach. Then, we deploy PARSY-VDD on both commercial single-core (STM32 family) and a specific multi-core (GAP9) edge device. We introduce an architecture-agnostic algorithmic optimization for SysId, improving the execution by 90× and reducing the consumption by 85× compared with the state-of-the-art SysId implementation on GAP9. Results show that by utilizing the unique parallel computing capabilities of GAP9, the execution time is 751 μ s with the high-performance multi-core solution operating at 370MHz and 0.8V, while the energy consumption is 37 μ J with the low-power solution operating at 240MHz and 0.65V. Compared with other single-core implementations based on STM32 microcontrollers, the GAP9 high-performance configuration is 76× faster, while the low-power configuration is 360× more energy efficient.

Authors

Institutions

Publication Details

Journal
IEEE Internet of Things Journal
Published
2025-04-08
DOI
https://doi.org/10.1109/jiot.2025.3558365
Primary Topic
Integrated Circuits and Semiconductor Failure Analysis
Type
article
Field-Weighted Citation Impact
0.00
Controls
|||
ALL TIME
JAN
FEB
MAR
APR
MAY
JUN
JUL
AUG
SEP
OCT
article

Parallelization is All System Identification Needs: End-to-End Vibration Diagnostics on a Multicore RISC-V Edge Device

Giuseppe Tagliavini, Amirhossein Moallemi, Davide Rossi, Davide Brunelli et al.
IEEE Internet of Things Journal
Integrated Circuits and Semiconductor Failure Analysis
article

Parallelization is All System Identification Needs: End-to-End Vibration Diagnostics on a Multicore RISC-V Edge Device

Giuseppe Tagliavini, Amirhossein Moallemi, Davide Rossi, Davide Brunelli, Federica Zonzini, Amirhossein Kiamarzi
article en

Abstract

The early detection of structural malfunctions requires the installation of real-time monitoring systems ensuring continuous access to the damage-sensitive information; nevertheless, it can generate bottlenecks in terms of bandwidth and storage. Deploying data reduction techniques at the edge is recognized as a proficient solution to reduce the systemfs network traffic. However, the most effective solutions currently employed for the purpose are typically based on memory and power-hungry algorithms, making their embedding on resourceconstrained devices very challenging; this is the case of vibration data reduction based on System Identification (SysId) models. This paper presents PARSY-VDD, a fully optimized PArallel end-to-end software framework based on SYstem identification for Vibration-based Damage Detection, as a suitable solution to perform damage detection at the edge in a time and energyefficient manner, avoiding streaming raw data to the cloud. First, we evaluate the damage detection capabilities of PARSYVDD with two benchmarks: a bridge and a wind turbine blade, showcasing the robustness of the end-to-end approach. Then, we deploy PARSY-VDD on both commercial single-core (STM32 family) and a specific multi-core (GAP9) edge device. We introduce an architecture-agnostic algorithmic optimization for SysId, improving the execution by 90× and reducing the consumption by 85× compared with the state-of-the-art SysId implementation on GAP9. Results show that by utilizing the unique parallel computing capabilities of GAP9, the execution time is 751 μ s with the high-performance multi-core solution operating at 370MHz and 0.8V, while the energy consumption is 37 μ J with the low-power solution operating at 240MHz and 0.65V. Compared with other single-core implementations based on STM32 microcontrollers, the GAP9 high-performance configuration is 76× faster, while the low-power configuration is 360× more energy efficient.

IEEE Internet of Things JournalVol. 12(13)
University of Bologna (IT)
Openalex Percentile: Top 94%
Integrated Circuits and Semiconductor Failure Analysis
AI Navigator

Ask Laika to Summarize, Analyze, and Connect papers live on the map.

Summarize Papers & Methodologies

Extract key findings, datasets, and comparative methods across publications.

Benchmark Rankings & Visual Analytics

Rank top research institutions, authors, funders, topics, and journals by Field-Weighted Citation Impact (FWCI) and paper volume with instant charts.

Connect Distant Disciplines

Bridge topological clusters on the map to find hidden collaborative intersections.