Thermal Management of TSV Array in 3D Integrated Circuits Based on the Super-Element Method

As Moores Law approaches its physical limits, three-dimensional integrated circuits (3D ICs) utilizing Through- Silicon Vias (TSVs) are gradually replacing traditional two-dimensional integrated circuits (2D ICs). However, the highly integrated circuits also introduce more significant thermal issues. In this paper, an optimization method for the positions of multiple heat sources in the TSV array is proposed to minimize the temperature and temperature gradient within the model. This study employs super-element methods for thermal simulations, leverages the superposition principle to reduce the computational cost, and utilizes Simulated Annealing (SA) for position optimization. Experimental results show that the time required for the super-element method to compute the simulation model is approximately 26.4% of that required by FEM. Furthermore, after optimization, the maximum temperature rise, average temperature rise, and temperature gradient of the TSV array are reduced by 4.58%, 0.64%, and 3.78%, respectively, significantly mitigating the thermal effects on the circuit.