Neural Network Optimization Framework for NPU-MCU Heterogeneous Platforms

With the widespread application of Deep Neural Networks (DNNs) in edge computing and embedded systems, edge devices face challenges such as limited computational resources and strict power constraints. Microcontroller Units (MCUs), combined with the low-cost and mass-production advantages of dedicated Neural Processing Units (NPUs), provide a more practical solution for edge AI. This paper proposes a neural network optimization framework for NPU-MCU heterogeneous computing platforms. By leveraging techniques such as algorithm partitioning, pipeline design, data flow optimization, and task scheduling, the framework fully exploits the computational advantages of NPUs and the control capabilities of MCUs, significantly improving the system's computational efficiency and energy efficiency. Specifically, the framework assigns compute-intensive tasks (e.g., convolution, matrix multiplication) to NPUs and control-intensive tasks (e.g., task scheduling, data preprocessing) to MCUs. Combined with pipeline design and data flow optimization, it maximizes hardware resource utilization, reduces power consumption, and alleviates memory bandwidth pressure. Experimental results demonstrate that the framework performs exceptionally well in edge computing and IoT devices, effectively addressing the challenges of deploying neural networks in resource-constrained scenarios. This research provides a systematic optimization method for the industrial application of edge intelligence, offering significant theoretical and practical value.