RISC-V compatible CPU for intermittently driven circuit

Power obtained from ultra-small energy harvesters is often tiny and difficult to use. The circuits with high power consumption can be driven by temporarily storing that power in a capacitor for a long time and discharging it instantaneously. We propose a unique intermittent-drive CPU that can operate even if the supplied power is minimal and intermittent. Regular CPUs are reset when power is turned off, so they are reset after every intermittent drive. This is because the regular CPU assumes a stable power supply. To enable intermittent and low-power operation, the amount of power required for CPU operation consumed at one time is reduced by executing only one CPU instruction cycle at a time. After instruction cycle processing, only the information necessary to continue the operation is stored in nonvolatile memory and read back when needed in subsequent cycles. This method does not save all data simultaneously, as in the sleep operation, but saves the data by dividing it frequently. Therefore, it has the advantage of low instantaneous power consumption and does not require special devices such as nonvolatile Flip Flops. We implemented an intermittent-drive CPU using the RISC-V RV32I instruction set architecture on an FPGA and a chip fabricated in a 0.18 um standard CMOS process. The designed chip was intermittently driven successfully with 6kHz power and reset signal.