920-MHz Fully-Integrated LNA Operated in Moderate-Inversion Region

Low-noise, low-current consumption, and high-linearity 920-MHz fully-integrated cascode LNA operated under moderate-inversion region is presented. To obtain low-noise characteristics using an integrated poor-Q-factor on-chip inductor, a transistor operating under moderate inversion was found to be optimal since the inductance of the input inductor can be reduced. Furthermore, the moderate inversion operation presents low current consumption. However, the odd-order transconductance of the MOSFET operating under the moderate-inversion region induced poor linearity, which improved the gate width and gate bias optimization of the cascode MOSFET. The measurement results include an |s21| of 14.0 dB, NF of 2.10 dB, and -5.2 dBm IIP3 with current consumption of 1.6 mA. The process technology used in this study was the TSMC 180 nm CMOS technology.