Offset-Tolerant Body-Biased Sense Amplifier With Rise-Time Control Technique for SRAM

In this paper, we propose an Offset-Tolerant Bodybiased sense amplifier (OTB-SA) with a rise-time (TRISE) control technique to address the sensing failure issue that occurs when the input voltage difference (DVBL) of a latch-type SA is smaller than the offset voltage (VOS). The OTB-SA with TRISE leverages body biasing and TRISE control to enhance the differential signal injection (DSI) effect, thereby reducing both VOS and energy consumption. Post-layout HSPICE simulation results using a 28 nm technology model indicate that, when target VOS standard deviation (sOS) is 5 mV, the OTB-SA with TRISE achieves a 49.6 reduction in area and a 60.1% decrease in energy consumption compared to a voltage-latched SA (VLSA) without TRISE. Moreover, compared to previous SAs, the OTB-SA with TRISE showed up to 69.1% area reduction and up to 91.2% energy consumption reduction. Measurements from a 28 nm test chip confirmed that TRISE control is effective, showing a trend where sOS decreases as TRISE increases for OTB-SA.