Microwave Power Performance of Buffer-Free AlGaN/GaN MISHEMT With MOCVD Grown Ex Situ SiN
This work investigates the effect of ex situ MOCVD-grown SiN<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> gate dielectric and PECVD SiN<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> passivation layer on the microwave power performance of buffer-free AlGaN/GaN MISHEMT. We fabricated devices on a series of four samples diced from a 4 inch epi: first two samples had no gate dielectric while the latter two had upto 3 nm of ex situ SiN<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> as the gate dielectric. In each of the categories, one sample had baseline 100 nm SiN<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> passivation deposited under high frequency plasma conditions, while the other sample had 100 nm bilayer SiN<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</i> passivation. Devices had gate length of 0.22 μm and width of 2 × 50 μm. Samples with no gate dielectric exhibited low 2DEG density ~7 × 10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>12</roman></sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>2</roman></sup> possibly due to significant charge depletion by the gate Fermi pinning owing to a thin barrier (10 nm, Al<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.3</roman></sub>Ga<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>0.7</roman></sub>N). Moreover, these HEMTs exhibited high current collapse (CC) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\ge$</tex-math></inline-formula>38% irrespective of the passivation scheme when subjected to 1 μs pulse. The MISHEMTs on the other hand, exhibited high 2DEG density ~10<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><roman>13</roman></sup> cm<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-<roman>2</roman></sup> which also manifested as increased threshold voltage. Gate lag reduced to a mere 4%–6% in MISHEMTs, while under gate–drain double pulsing, the collapse was found to be 27% and 11% for different passivation schemes. Drain current transient (DCT) studies revealed suppression of surface states upon ex situ SiN deposition, and hinted at localized defects. Finally, under 28 V Class B operation at 6 and 10 GHz, output power of 8.1 W/mm power added efficiency (PAE 68%) and 5.2 W/mm (PAE 47%) respectively were measured under pulsed loadpull conditions.
Authors
- Digbijoy N. Nath (ORCID: https://orcid.org/0000-0003-0669-0033)
- Aditya Sadhanala (ORCID: https://orcid.org/0000-0003-2832-4894)
- Aniruddhan Gowrisankar (ORCID: https://orcid.org/0000-0002-8399-0817)
- Hareesh Chandrasekar (ORCID: https://orcid.org/0000-0001-7881-3739)
- Sai Charan Vanjari (ORCID: https://orcid.org/0000-0003-4448-4943)
- Rasika Muralidharan (ORCID: https://orcid.org/0009-0002-0362-4890)
- Rijo Baby (ORCID: https://orcid.org/0000-0002-8754-0637)
- Ashu K. Bansal (ORCID: https://orcid.org/0009-0002-7789-1123)
- Srinivasan Raghavan (ORCID: https://orcid.org/0000-0003-2503-8606)
Institutions
- Indian Institute of Science Bangalore (IN)
- Cypress Semiconductor Corporation (Japan) (JP)
Publication Details
- Journal
- IEEE Transactions on Electron Devices
- Published
- 2025-04-07
- DOI
- https://doi.org/10.1109/ted.2025.3554160
- Citations
- 2
- Primary Topic
- GaN-based semiconductor devices and materials
- Type
- article
- Field-Weighted Citation Impact
- 2.52
Funders
- Ministry of Electronics and Information technology