Adaptive and Passage-Based Fault-Tolerant Routing Methods for Three-Dimensional Mesh NoCs

This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, a detour direction is statically defined for each faulty region. Due to the long detour path and the use of eight virtual channels, this method has the problems of high communication latency and a large hardware overhead. To solve these problems, the first proposed method allows adaptive detours for faulty regions, and the second proposed method allows the passage of them. The simulation results show that, compared with the existing method, the second proposed method enables us to reduce the latency by about 30% and improve the throughput by about 3.1% with half of the virtual channels.

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Publication Details

Journal
Chips
Published
2025-04-06
DOI
https://doi.org/10.3390/chips4020014
Citations
1
Primary Topic
Advanced Memory and Neural Computing
Type
article
Field-Weighted Citation Impact
0.73
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article

Adaptive and Passage-Based Fault-Tolerant Routing Methods for Three-Dimensional Mesh NoCs

Yota Kurokawa, Masaru Fukushi
1 citations
Chips
Advanced Memory and Neural Computing
0.73
article

Adaptive and Passage-Based Fault-Tolerant Routing Methods for Three-Dimensional Mesh NoCs

Yota Kurokawa, Masaru Fukushi
article en
1 citations

Abstract

This paper proposes novel two fault-tolerant routing methods for a 3D mesh network-on-chip (NoC). The existing method proposed by Boppana et al. combines two routing methods, minimal fully adaptive routing and fault-tolerant routing, for faulty region detouring. However, in the latter fault-tolerant routing, a detour direction is statically defined for each faulty region. Due to the long detour path and the use of eight virtual channels, this method has the problems of high communication latency and a large hardware overhead. To solve these problems, the first proposed method allows adaptive detours for faulty regions, and the second proposed method allows the passage of them. The simulation results show that, compared with the existing method, the second proposed method enables us to reduce the latency by about 30% and improve the throughput by about 3.1% with half of the virtual channels.

ChipsVol. 4(2)
Yamaguchi University (JP)
Openalex Percentile: Top 30%
Advanced Memory and Neural Computing
0.73
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