RPFF-PA : Reliable and Parallel Fault-tolerant Framework for Path Latency Reduction Deployed in Register Arrays

Soft errors can lead to electronic device failures caused by radiation events. Therefore, fault-tolerant designs are essential for safeguarding critical memory components and processors. The N-modular redundancy (NMR) scheme presents a practical means of implementing register protection. However, the NMR fault-tolerant scheme is serially configured on the critical path, increasing path latency of approximately 12.4 \(\% \) -35.5 \(\% \) . In this paper, we propose a parallel fault-tolerant framework for register arrays(RPFF-PA), which realizes the parallelized execution of hardern processes and read/write operations. By executing the decoding process in parallel with the decision circuit, the latency cost caused by fault-tolerant components is significantly reduced. The results demonstrate that the strategy reduces path latency by 5.2 \(\% \) -20.3 \(\% \) compared to the original NMR approach. Furthermore, the framework includes a real-time error correction module capable of effectively addressing the error accumulation issue, thereby enhancing the reliability of the fault-tolerant system.