An Energy‐Efficient Half‐Select Disturb‐Free Near‐Threshold Differential VGND 10 T SRAM Cell

ABSTRACT This paper introduces a new static random‐access memory (SRAM) cell, the Differential Virtual Ground (VGND) 10 T (Dvgnd10T), designed for superior performance. By employing a configuration that consistently maintains the VGND voltage below the threshold of an NMOS transistor, this approach minimizes power consumption and eliminates the risk of half‐select disturbance during near‐threshold voltage operation. Additionally, the integration of a cut‐off supply voltage technique significantly improves the writability of the cell. Simulation outcomes in a 32‐nm CMOS technology demonstrate that the Dvgnd10T cell enhances read stability and writability by 3.6× and 1.8×, respectively, over traditional 6T cells. Furthermore, the write and read energy requirements are improved by 1.032× and 1.86× compared to 6T cells. The leakage power of the proposed cell is reduced by 2.24× compared to the 6T cell, while occupying 1.75× more silicon area. The proposed cell improves the overall Figure of Merit (FOM) by 13.2× compared to the 6T cell.