First write pulse-induced interface damage in ferroelectric field-effect transistors

We report the first direct experimental evidence that the first write pulse (cycle 1) generates more than half of the total traps generated until the complete collapse of the memory window at cycle $10^{4}-10^{5}$, in ferroelectric field effect transistors (FEFETs). This conclusion is reached by tracking the generated traps by a combination of subthreshold slope and charge pumping measurements in a Ferroelectric field-effect transistor and an equivalent standard MOSFET of same effective oxide thickness (EOT). We also find that with continued cycling, traps get generated more toward the bulk of the stack away from the Si/SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface. We show that: (1) the first switch effect leads to nearly 50% of the total trap density $\left(\mathrm{N}_{i t}\right)$ near the Si/SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface until memory window closure (2) with further bipolar cycling, damage happens both at and away from Si/SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> interface.