Loop‐Unrolled SAR ADC With Complementary Voltage‐to‐Time Converters

ABSTRACT A 6‐bit asynchronous loop‐unrolled (LU) successive approximation register (SAR) analogue‐to‐digital converter (ADC) with a complementary voltage‐to‐time converter (CVTC) and the efficient latch technique needed for this structure are proposed. The proposed structure utilises CVTC to reduce the power consumed by the reset operation and halves the operating frequency of the CVTC. Designed with a 500‐nm CMOS process, the 6‐bit 10‐MS/s LU SAR ADC shows a power saving of 23.66% compared to the VTC‐based LU SAR ADC.