Temperature Sensitivity Assessment of Nonlinear Channel Tunnel Field-Effect Transistor for Raised Efficiency and Reliability in Nanoscale Electronics

This article presents a thorough assessment of linearity for the Dual Metal Step Channel Heterojunction Negative Capacitance Double Gate Tunnel Field Effect Transistor (SC-HDM-TFET) for the temperature range of 200K to 500K. The SC-HDM-TFET's special dual metal gate, step channel and heterojunction provides better electrostatic control and increased tunneling efficiency. However temperature changes can considerably stimulus the mobility of the carriers, band-to-band tunneling (BTBT) rates by causing 2nd and 3rd order harmonic distortion (HD2 & HD3), intermodulation distortion (IMD3), and input-referred third-order intercept point (IIP3) and 2nd and 3rd order voltage intercept points (VIP2 & VIP3). Device linearity performance is assessed systematically for the specified range of temperature. SILVACO TCAD-2D is used for the device simulations and focus on the temperature-dependent behavior of the proposed device. From the results it is very clear that the SC-HDM-TFET's dual metal layout and step channel design both work together to reduce thermal deterioration and provide exceptional linearity stability even at elevated temperatures. This study demonstrates the SC-HDM-TFET's resilience for use in demanding thermal conditions, guaranteeing dependable operation in electronic systems of the future.