A Low-Power Two-Step Hold-and-Go Counter Without Calibration for Single-Slope ADC in CMOS Image Sensors

In traditional two-step (TS) counters, the absence of a direct connection between coarse and fine quantization counters necessitates an error calibration block, complicating circuit and timing design. To solve the problem, this paper proposes a TS hold-and-go double-data-rate (TS-HG-DDR) counter for column low-power single-slope analog-to-digital converter (SS ADC) in CMOS image sensors. A TS counting logic with an HG algorithm is proposed, allowing the counter to selectively operate in either ([Formula: see text])-bit fine or M-bit coarse quantization modes without calibration. With the HG algorithm, the counter implements digital correlated double sampling without additional modules such as a bit-wise inversion (BWI) structure, thereby reducing the area. Moreover, a DDR structure that only records the parity information is employed to reduce power consumption. The TS-HG-DDR counter is implemented in a 10-bit column-parallel SS ADC using a 55[Formula: see text]nm CMOS process, with 2.5[Formula: see text]V analog and 1.2[Formula: see text]V digital supplies. As a result, the TS-HG-DDR counter achieves a power consumption reduction of up to 32.6% compared to a TS-BWI counter. The SS ADC has a total power consumption of 27.4[Formula: see text] [Formula: see text]W, with the proposed counter consuming 0.77[Formula: see text] [Formula: see text]W. The differential and integral nonlinearities of the SS ADC are +0.36/[Formula: see text]0.38 LSB and +0.52/[Formula: see text]0.95 LSB, respectively.