Innovative Fault Detection for AES in Embedded Systems: Advancing Resilient and Sustainable Digital Security

The AES algorithm is commonly used in embedded systems for security purposes, but its robustness can be compromised by natural and malicious faults, leading to potential information leakage. Various fault detection schemes have been proposed to protect it against differential fault analysis attacks. These schemes aim to detect and mitigate any potential vulnerabilities in the AES algorithm, ensuring system security. The implementation of fault detection schemes aligns with Sustainable Development Goal (SDG) 9, which focuses on building resilient infrastructure and promoting inclusive and sustainable industrialization. Enhancing the security of embedded systems through these measures contributes to creating a more secure and sustainable digital environment for all. This study introduces a new fault-parity detection scheme that involves comparing the correct parity of the rounded output with the predicted parity based on AES processing steps. The strengths and weaknesses of this scheme in defending against fault attacks are also discussed. The experimental results demonstrate that the proposed fault detection scheme achieves an impressive fault coverage of 99.999%. Implemented on the Xilinx Virtex-5 FPGA, the scheme was compared to existing methods in terms of fault coverage, area overhead, frequency degradation, and throughput. These results highlight the ability of the proposed scheme to strike a balance between implementation cost and AES security.