Layout Design Strategies for Scaling Down Semiconductor Systems Based on Current Flow Analysis in Interconnect

As the demand for high-density integrated circuits increases, scaling down devices has already reached its limit, making the optimization of interconnect–via layout an important research challenge. Conventional semiconductor design adopts conservative margins to ensure process reliability, but this often results in inefficient space utilization and degraded electrical performance. This study evaluates the possibility of optimizing design rules by analyzing the impact of reduced contact area in interconnect–via structures on the current flow and resistance. Finite element method analysis (FEM) using Ansys Workbench revealed that current is concentrated in approximately 20% of the interconnect height and the diagonal region of the via. A resistance model reflecting this current distribution demonstrated high accuracy, with an error range of 1–3% compared to simulation results. Resistance measurements of various fabricated structures produced through photolithography and lift-off processes showed a significant increase in resistance when the contact area was reduced to 50% or less, consistent with simulation results. This study demonstrates the potential to optimize both space utilization and electrical performance by minimizing the conservative margins between interconnects and vias, contributing to next-generation high-density integrated circuit design.