Diamond thermal matrix demonstration for two-tier 3D integrated circuits

A diamond matrix scaffold is crucial for 3D dense chips because it provides exceptional thermal management due to its excellent thermal conductivity. Diamond can also replace copper thermal vias, enabling efficient heat transfer and improved cooling performance. Its low thermal boundary resistance with Si and dielectrics (such as SiO2) ensures minimal thermal bottlenecks, enhancing the 3D chip’s overall thermal management and reliability. For the first time, we have demonstrated a BEOL-compatible two-tier diamond matrix scaffold experimentally in combination with SiO2 and on top of a Si wafer. The diamond was nucleated and grown conformally in the via holes with 1:3, 1:2, 1:1, and 2:1 (width:height) aspect ratios to form the via. A relatively low residual stress of 0.35–0.9 GPa and an FWHM as low as 4.3 cm−1 were measured using Raman spectroscopy. The (111) plane was measured as the dominating plane after the growth on top, while the (110) plane was the dominating plane inside the trenches mid-growth. This highly thermally conductive diamond matrix (thermal conductivity between 500 and 1800 W/m/K) can be used not only for Si technology but also for GaN and Ga3O2 technologies to push the boundaries of output power by lowering the junction/channel temperature.