Investigation of Heterojunction Bipolar Transistor Reliability for Analog and RF Applications

Heterojunction Bipolar Transistor is now widely used in high-speed RF and analog applications due to their superior noise figure performance and high transconductance. Driven by the requirement of higher power, it results in usage with higher current density and voltage excursion, thus reliability must be carefully analyzed to guarantee the robustness of the application. After a brief review of the physical mechanism of the degradation that can be characterized in a standard DC stress, a dedicated test structure is presented to perform AC stress at 500 MHz with a square signal in High Temperature Operating Life (HTOL) environment. Several stress conditions and device geometry are analyzed. A comparison with DC stress at wafer level is presented. Then, RF stress measurement is presented in a load-Pull environment. A power amplifier cascode stage is investigated for different stress conditions. The contribution of the contact degradation of RF probe is highlighted and it is shown that after a re-contact major performance degradation is recovered. RF ageing simulation is also presented, and it comes out that when using a quasistatic assumption for the degradation, the gain degradation, as provided by simulation, is slightly pessimistic. Some relaxation and recovery effects could be implied to explain these results. Finaly the same power stage is stressed during 168 h either at a constant input power or during a sweep of supply, but also in an aggressive load mismatch condition. Conclusions drawn by the experiments show a very good device robustness in RF stress application.