Activity Compatible Device-to-Circuit Framework for Process, BTI and HCD Variability

A simulation framework is developed to analyze FET level process, BTI, and HCD variability impact on circuits. The relative contributions of process versus aging variation and that of BTI and HCD of $\mathbf{p}$ - and $\mathbf{n -}$ FETs are studied. The framework uses physical BTI and HCD models, which enables simulation of random data-path like input activity. Circuit level variability is shown to be dependent on input gate excitations (history), which cannot be replicated using RO like benchmark simulations. The requirement of cycle-by-cycle circuit simulation is highlighted.