A Device-to-Circuit Aging Framework to Study NBTI Process Dependence

NBTI time kinetics is measured in p-FETs having different architectures (FinFETs and GAA SNS FETs), channel materials (Si and SiGe) and gate stack processes and is analyzed using the BAT modeling framework. The relative contributions due to generated interface and bulk traps and hole trapping in process related pre-existing bulk traps on the device parametric shift are determined at different gate bias and temperature, at short-time stress and End-of-Life. The CARAT framework is used to simulate frequency shift in RO circuits at different fixed bias and temperature, and for Dynamic Voltage and Frequency Scaling without and with Self Heating effect. Differences in the device architecture and channel material show different impact on circuit aging at normal versus overclocking usage conditions. Gate insulator process optimization shows reduce aging under overclocking usage conditions.