Epitaxy fine tuning to improve trench power MOSFET avalanche reliability

In this paper, we present a comprehensive study on reliability of Shielded Gate power MOSFET (SG-MOSFET) in avalanche regime. The relation between the sensitive charge balance and drain to source breakdown voltage ($\mathrm{BV}_{\mathrm{dss}}$) is analyzed through TCAD simulations and electrical characterization. Thanks to the improved calibration of our simulations, we could target a limited area in the drift region of the SGMOSFET architecture, that is responsible for the stability of $B V_{\text {dss }}$. We propose a fine tuning of epitaxy recipe to engineer the localization of the electric field peak at the bottom of the trench during avalanche stress. Furthermore, this proposal is implemented on silicon wafers and we demonstrate its validity and the improved reliability of SG-MOSFET structure, through electrical characterization results, in terms of: $\mathbf{B V} V_{\text {dss }}$ during avalanche current drain stress; ON-state Resistance ($\mathrm{R}_{\mathrm{dsON}}$); and energy capability during Clamped Inductive Switch (CIS) tests.