Detection and qualification of well charging originating from plasma processing induced charging damage – PID (invited)

Product fails caused by charging of isolated well configurations from plasma processing induced charging damage (PID) are reported in the literature along with recent comprehensive reliability assessments to get an insight into this neglected PID failure mode. This work will summarize the published results of the various well charging cases, describe an appropriate qualification strategy and discuss the different approaches for the implementation of a design rule check. While so far, all experimental PID well charging data in the literature have been collected from technologies with SiO<inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> as MOS gate dielectric, reliability data are presented in this work from MOS transistors with a high-K dielectric for the first time. The efficiency of various protection elements against well charging is also debated and how a protection element and its size can be incorporated into a design rule.