Demonstration of Vertically Stacked ZnO/Te Complementary Field‐Effect Transistor

Abstract The complementary field‐effect transistor (CFET) structure is a highly area‐efficient technology. However, their fabrication entails highly complex integration processes using wafer transfer or recrystallization, which has been limiting further development. In this paper, an alternative method is proposed to realize CFETs using p‐type tellurium (Te) (for the lower‐level channel) and n‐type zinc oxide (ZnO) (for the upper‐level channel). Te and ZnO are directly deposited on a 30 × 30 mm 2 SiO 2 /Silicon substrate, using a considerably low‐temperature fabrication process (<150 °C). The lower p‐type channel exhibits superior mobility exceeding 10 cm 2 V −1 s −1 even after the integration of the entire CFET process. The CFET inverter demonstrates a voltage gain >51 at V DD = 4 V and noise margins of 0.36 and 0.45 V at V DD = 1 V. Using the same integration process, functional NAND and NOR logic gates are successfully demonstrated in the vertically integrated CFET structure. The proposed ZnO/Te CFET can be a promising device technology, particularly for 3D and heterojunction integration requiring a low thermal budget.