Test and Diagnosis Strategies for Interchiplet Interconnects

The irregular through-silicon via (TSV) layout complicates the crosstalk’s effect, making parallel testing more difficult. For efficient testing and diagnosis of irregular TSV layouts in postbonding, a novel test grouping algorithm based on neural networks is proposed. The influence range of crosstalk faults and the hardware overhead are both considered in the algorithm, maximizing the number of TSVs that can be tested simultaneously, thereby shortening both the test and diagnosis time. Based on the grouping results, an efficient built-in self-test (BIST) architecture with low hardware overhead for testing and diagnosing TSVs is proposed. Die wrapper register (DWR) cells of the IEEE Std 1838 are enhanced and diagnosis is embedded into the test process by improving test patterns and using an on-chip feature compression circuit. This approach supports testing, locating, and identifying stuck-at, bridge, delay, and crosstalk faults. Experimental results show that the test grouping algorithm reduces the average number of groups by 0.371, with more significant reductions observed in large-scale and highly complex settings. The proposed architecture achieves shorter test and diagnosis time to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$7G+GN$ </tex-math></inline-formula> with lower hardware overhead, where G and N are the number of groups and TSVs, respectively.