CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-<i>k</i> Dielectric van der Waals Encapsulation

Two-dimensional (2D) semiconductors are potential candidates for advanced technology nodes, but their integration with silicon lines remains a significant challenge. Here, we present a high-<i>k</i> dielectric van der Waals encapsulation strategy for the fabrication of 2D semiconductor-based complementary field-effect transistors (CFETs) compatible with established processes. This technique, involving the transfer of a high-<i>k</i> dielectric onto 2D semiconductors, protects channels from polymer contamination, enables O<sub>2</sub> plasma surface cleaning, and facilitates the following dielectric depositions without doping or damage. The strategy results in heterostructures and devices with reduced surface roughness and is applicable to both p- and n-type semiconductors, including MoS<sub>2</sub>, WS<sub>2</sub>, MoTe<sub>2</sub>, and black phosphorus. Utilizing this method, we have successfully fabricated 2D CFET inverters with a gain of up to 19.54 and power consumption as low as 2.63 nW. Our work paves the way for the integration of 2D semiconductors with silicon technology, therefore accelerating the lab-to-fab transition progress.

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Publication Details

Journal
Nano Letters
Published
2025-04-03
DOI
https://doi.org/10.1021/acs.nanolett.5c00220
Citations
6
Primary Topic
Graphene research and applications
Type
article
Field-Weighted Citation Impact
3.11

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article

CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation

Yuchen Cai, Y.-N. Wang, Jun He, Jia Lin et al.
6 citations
Nano Letters
Graphene research and applications
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article

CMOS-Compatible Fabrication of 2D Semiconductor-Based CFETs via High-k Dielectric van der Waals Encapsulation

Yuchen Cai, Y.-N. Wang, Jun He, Jia Lin, Fuyuan Zhang, Yujia Yan, Kai Xu, Tao Yan, Shu‐Hui Li, Xiaolin Liu, Zhenxing Wang, Feng Wang, Yuhan Zhu, Xueying Zhan
article en
6 citations

Abstract

Two-dimensional (2D) semiconductors are potential candidates for advanced technology nodes, but their integration with silicon lines remains a significant challenge. Here, we present a high-<i>k</i> dielectric van der Waals encapsulation strategy for the fabrication of 2D semiconductor-based complementary field-effect transistors (CFETs) compatible with established processes. This technique, involving the transfer of a high-<i>k</i> dielectric onto 2D semiconductors, protects channels from polymer contamination, enables O<sub>2</sub> plasma surface cleaning, and facilitates the following dielectric depositions without doping or damage. The strategy results in heterostructures and devices with reduced surface roughness and is applicable to both p- and n-type semiconductors, including MoS<sub>2</sub>, WS<sub>2</sub>, MoTe<sub>2</sub>, and black phosphorus. Utilizing this method, we have successfully fabricated 2D CFET inverters with a gain of up to 19.54 and power consumption as low as 2.63 nW. Our work paves the way for the integration of 2D semiconductors with silicon technology, therefore accelerating the lab-to-fab transition progress.

Nano LettersVol. 25(15)
Chinese Academy of Sciences (CN), Shanghai University of Electric Power (CN), Center for NanoScience (DE), Wuhan University (CN), Henan Academy of Sciences (CN), FZU ‒ Institute of Physics of the Academy of Sciences of the Czech Republic (CZ), National Center for Nanoscience and Technology (CN), Institute of Semiconductors (CN), National Laboratory for Superconductivity (CN), University of Chinese Academy of Sciences (CN), Zhejiang University (CN)
National Natural Science Foundation of China, Chinese Academy of Sciences, Key Laboratory of Nanosystem and Hierarchical Fabrication, Chinese Academy of Sciences, National Key Research and Development Program of China
Openalex Percentile: Top 9%
Graphene research and applications
3.11
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