Algorithmic-Level Design Partitioning for Latency Minimization in Multi-Chip and Multi-Die Systems

In the post-Moore’s Law era, multi-chip and chiplet designs have become important trends. However, due to the limited inter-chip routing resources and large delays, partition a design into such multi-chips may lead to performance degradation. Existing netlist-based partitioning algorithms mostly targeting for cut size minimization do not handle performance well. In this article, we propose an Integer Linear Programming (ILP)-based algorithmic-level design partitioning algorithm for latency minimization. Our ILP formulation considers both partition resource constraints and inter-chip routing resource constraints. Multi-cycle communication is considered to address large inter-chip delay, together with local cache design for inter-chip data transmission bandwidth. For 2.5D FPGAs, our approach can improve the final clock frequency by 74.3% and circuit runtime by 60.2% when compared to Vivado. For multi-FPGA systems, we achieve 5 to 29 times higher clock frequency and an average of 11 times better performance over Synopsys HAPS software.