An ultra-low power SNN co-processor based on differential-pair SRAM and memristive memory with reconfigurable computing-in-memory array and coding scheme

Abstract This paper presents an ultra-low-power spiking neural network co-processor (RSNNP) with a reconfigurable computing-in-memory (CiM) cell array, leveraging both differential-pair SRAM and memristive memory. The proposed RSNNP introduces adaptability through three reconfigurable strategies: supporting both volatile (SRAM) and non-volatile (memristive) memory cell, free-extending the CiM array scale, and flexible-switching between rate and temporal coding schemes. A prototype chip, fabricated using 55 nm technology, achieves exceptional efficiency, with power consumption as low as 0.057 μW (@SRAM) and 0.0102 μW (@memristive) for a 24 fps image recognition task. Experimental results demonstrate the RSNNP’s superiority in adapting to different SNN tasks and outperforming state-of-the-art SNN processors in power efficiency with lower power consumption. This work marks a significant step toward energy-efficient and adaptable SNN computation, suitable for edge computing and neuromorphic hardware applications.