A resilient, high-performance, low-power 11T CNTFET SRAM cell for IoT implementations

Abstract Current system-on-chips need robust, economical SRAM cells since energy sources are limited and technology is scaling. Hence, a resilient, delay and energy-optimized 11T CNTFET SRAM design is suggested in this analysis. The suggested High—Performance, Low—Power 11 Transistors (HPLP11T) CNTFET SRAM design features a resilient interlinked design featuring a conventional inverter paired with a cascaded CNTFET transistor, along with a Schmitt-based inverter that utilizes a pull-up transistor of twice the normal length. Isolating internal memory units from the read path completely eradicates read disturbance Additionally, employing a write-assist technique, the writing process executes in a pseudo-differential manner using a write bit line and a control signal. To assess the efficacy of the suggested HPLP11T CNTFET SRAM design, it is evaluated against alternative existing 11T SRAM cells through simulation conducted using the HSPICE tool, employing the Stanford University 32 nm CNTFET technology. The evaluation was conducted under extreme conditions, considering a 0.9 V supply voltage and accounting for challenging manufacturing processes, voltage fluctuations, and temperature variations (PVT). The intended HPLP11T CNTFET SRAM design demonstrates a write power of 1.584 nW, hold power of 4.563 nW, read power of 0.00457 μW, WSNM of 450 mV, HSNM of 360.8 mV, RSNM of 360.8 mV, write delay of 0.2724 ns, and read delay of 0.0454 ns. The proposed HPLP11T CNTFET SRAM cell demonstrates efficiency and suitability for Internet of Things (IoT) devices due to its low power consumption, high speed, and compatibility with microcontrollers. This is attributed to the inherent properties of CNTFETs, which offer high electron mobility and low leakage currents, leading to reduced power consumption and enhanced performance. Additionally, the design of the HPLP11T SRAM cell incorporates a read-decoupled approach and a Schmitt-trigger inverter, further improving stability and power efficiency, making it well-suited for IoT applications.

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Publication Details

Journal
Physica Scripta
Published
2025-04-03
DOI
https://doi.org/10.1088/1402-4896/adc8e4
Citations
5
Primary Topic
Advancements in Semiconductor Devices and Circuit Design
Type
article
Field-Weighted Citation Impact
3.65
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article

A resilient, high-performance, low-power 11T CNTFET SRAM cell for IoT implementations

M. Pushpa, S. Subhashini, P. Raja, U. Jeethika
5 citations
Physica Scripta
Advancements in Semiconductor Devices and Circuit Design
3.65
article

A resilient, high-performance, low-power 11T CNTFET SRAM cell for IoT implementations

M. Pushpa, S. Subhashini, P. Raja, U. Jeethika
article en
5 citations

Abstract

Abstract Current system-on-chips need robust, economical SRAM cells since energy sources are limited and technology is scaling. Hence, a resilient, delay and energy-optimized 11T CNTFET SRAM design is suggested in this analysis. The suggested High—Performance, Low—Power 11 Transistors (HPLP11T) CNTFET SRAM design features a resilient interlinked design featuring a conventional inverter paired with a cascaded CNTFET transistor, along with a Schmitt-based inverter that utilizes a pull-up transistor of twice the normal length. Isolating internal memory units from the read path completely eradicates read disturbance Additionally, employing a write-assist technique, the writing process executes in a pseudo-differential manner using a write bit line and a control signal. To assess the efficacy of the suggested HPLP11T CNTFET SRAM design, it is evaluated against alternative existing 11T SRAM cells through simulation conducted using the HSPICE tool, employing the Stanford University 32 nm CNTFET technology. The evaluation was conducted under extreme conditions, considering a 0.9 V supply voltage and accounting for challenging manufacturing processes, voltage fluctuations, and temperature variations (PVT). The intended HPLP11T CNTFET SRAM design demonstrates a write power of 1.584 nW, hold power of 4.563 nW, read power of 0.00457 μW, WSNM of 450 mV, HSNM of 360.8 mV, RSNM of 360.8 mV, write delay of 0.2724 ns, and read delay of 0.0454 ns. The proposed HPLP11T CNTFET SRAM cell demonstrates efficiency and suitability for Internet of Things (IoT) devices due to its low power consumption, high speed, and compatibility with microcontrollers. This is attributed to the inherent properties of CNTFETs, which offer high electron mobility and low leakage currents, leading to reduced power consumption and enhanced performance. Additionally, the design of the HPLP11T SRAM cell incorporates a read-decoupled approach and a Schmitt-trigger inverter, further improving stability and power efficiency, making it well-suited for IoT applications.

Physica ScriptaVol. 100(5)
Sri Manakula Vinayagar Medical College and Hospital (IN)
Openalex Percentile: Top 7%
Advancements in Semiconductor Devices and Circuit Design
3.65
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