A Run-Time Configurable NTT Architecture for Homomorphic Encryption Based on 3D Algorithm

Homomorphic encryption (HE) allows computations on encrypted data without compromising data privacy, making it ideal for scenarios like privacy-preserving computing. The primary bottleneck within HE schemes is polynomial multiplication, which can be accelerated using the number theoretic transform (NTT). This paper proposes a run-time configurable (RTC) NTT/INTT accelerator supporting HE parameter sets based on the 3D NTT algorithm. A conflict-free memory access pattern is proposed to efficiently implement the 3D NTT algorithm without additional hardware units. Additionally, an on-the-fly twiddle factor generator (TFG) is proposed to optimize memory utilization for twiddle factors (TFs). The proposed design achieves significant improvements in performance and area efficiency compared to state-of-the-art FPGA implementations.

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Publication Details

Published
2024-09-23
DOI
https://doi.org/10.1109/hpec62836.2024.10938507
Primary Topic
Internet of Things and Social Network Interactions
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article
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article

A Run-Time Configurable NTT Architecture for Homomorphic Encryption Based on 3D Algorithm

Tao Su, Dihu Chen, Weicong Lu, Xiaojie Chen
1 links
Internet of Things and Social Network Interactions
article

A Run-Time Configurable NTT Architecture for Homomorphic Encryption Based on 3D Algorithm

Tao Su, Dihu Chen, Weicong Lu, Xiaojie Chen
article en

Abstract

Homomorphic encryption (HE) allows computations on encrypted data without compromising data privacy, making it ideal for scenarios like privacy-preserving computing. The primary bottleneck within HE schemes is polynomial multiplication, which can be accelerated using the number theoretic transform (NTT). This paper proposes a run-time configurable (RTC) NTT/INTT accelerator supporting HE parameter sets based on the 3D NTT algorithm. A conflict-free memory access pattern is proposed to efficiently implement the 3D NTT algorithm without additional hardware units. Additionally, an on-the-fly twiddle factor generator (TFG) is proposed to optimize memory utilization for twiddle factors (TFs). The proposed design achieves significant improvements in performance and area efficiency compared to state-of-the-art FPGA implementations.

Sun Yat-sen University (CN)
Openalex Percentile: Top 65%
Internet of Things and Social Network Interactions
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