A LOW POWER AND AREA REDUCTION MULTIPLIER IMPLEMENTATION USING VEDIC MATHEMATICS IN 16NM FINFET TECHNOLOGY

Signal processing application circuits are being used in various instruments and devices. The implementation of these algorithms is done in various devices. For ASICs CMOS were used for several decades, but these devices suffer from second order effects which will affect the overall system performance. To overcome this, the paper presents the design and implementation of a 4 bit Vedic multiplier using 16nm FinFET technology which removes the issues with second order effects. By integrating Gate Diffusion Input (GDI) logic, the proposed method significantly reduces transistor count while enhancing speed and power efficiency. The results demonstrate that the Vedic multiplier achieves superior performance, making it well-suited for high-speed digital signal processing applications.