IMPLEMENTATION OF SEGMENTED CURRENT STEERING DIGITAL TO ANALOG CONVERTER USING MEMORY LESS PIPELINE DYNAMIC DESIGN TECHNIQUE

In the era of 5g technology, it is needed to improve speed of the circuitry used in analog and digital hardware. Digital to analog conversion is an essential process, DAC is a vital circuitry utilized for the same in the electronic systems. Our proposed current-steering DAC (CS-DAC) offers suitability for both high speed and high-resolution requirements. This work claims memory less dynamic pipeline design technique and implementation of CS-DAC using pipeline technique. CS-DAC with and without memory-less dynamic pipeline design technique is implemented using 180nm Berkeley Short-Channel IGFET Model (BSIM) version 3.3 model file. The simulation results of CS-DAC with and without pipeline design technique also compared as well.