A reduced effort design, low power, extremely compact, CMOS ADC based on voltage-to-time converter

A low-effort, tiny, low-power, inverter-based Analog-to-Digital Converter (ADC) is proposed in this paper. Based on a Voltage-to-Time Converter (VTC), the architecture requires a minimum design adjustment of the core block to let it work across supply voltages down to 0.3 V. The operation is based on charging and discharging of a timing capacitor, which enables a square wave from a digital counter to be converted from voltage to pulse width as a function of the input voltage signal. In turn, the duty cycle makes counting an additional digital counter driven by a feasible ring oscillator. Post-layout simulations of the designed solution, which relies on TSMC 180 nm standard CMOS technology, show a Si area of 7200 µm 2 , a 6.8 ENOB, a power consumption of 409 nW, and a sample rate of 5 kS/s. These ADC’s extremely low voltage and low power features make it appropriate for energy-harvested Systems-on-Chips (SoCs) in biomedical and Internet of Things (IoT) applications.