PHARFF: A Pipeline-Based Graceful Live Migration and Checkpointing Framework for Achieving High Availability and Reliability in FPGA Applications on Cloud

FPGAs have long been used in cloud environments for hardware acceleration, significantly improving service speed. However, while performance benefits are well-established, managing FPGA applications remains a challenge. Specifically, ensuring high availability and reliability requires live migration and checkpointing of hardware state registers with minimal downtime. Existing approaches focus on reducing migration time, but this has inherent limits in minimizing downtime. In this work, we propose a pipeline-based live migration and checkpointing mechanism that decouples downtime from migration time, effectively reducing it to nearly zero. This approach is realized through a novel framework, PHARFF, which is demonstrated with four benchmark applications: systolic array-based Matrix Multiplication, SSearch, FIR filter, and AES-128. Results show that PHARFF achieves the highest service availability, with zero downtime and minimal checkpoint sizes (zero for memoryless applications). Compared to existing methods, our approach also improves design frequency by 16% and optimizes hardware resource utilization, reducing LUT requirements by 27% and minimizing register usage by 2.5 times.