CMOS-Enabled Energy-Efficient Reconfigurable Intelligent Surfaces for Next-Generation Wireless Communications

Reconfigurable Intelligent Surfaces (RISs) are a key enabler for next-generation wireless communications. However, the power consumption associated with tuning components remains a significant challenge. This letter presents a novel single-pole single-throw (SPST) switch designed and implemented using a 55 nm bulk CMOS process, achieving high energy efficiency with a low driving voltage. The design features a decoupled control port and RF path port, greatly simplifying the feeding network and enhancing integration flexibility. For verification, a 12.5 GHz RIS with 144 units prototype incorporating the proposed SPST switch was fabricated and measured. Experimental results demonstrate a wide-angle scanning range of ±50°, with a maximum array power consumption of only 0.44 mW and per-element power consumption as low as 3 μW—at least three orders of magnitude lower than traditional PIN-based RISs. This achievement sets a new benchmark for energy efficiency in RIS hardware, providing a cost-effective and scalable solution to enable large-scale deployment in future wireless communication systems.