Multilogic Sense Amplifier With a Circuit for Dynamic Reference Voltage Generation

The rapid development of artificial intelligence (AI) systems has engendered a considerable increase in the computational power required in data-intensive applications, including facial recognition and image processing applications. The conventional von Neumann architecture, in which large quantities of data are transmitted between processing units and memory units, creates a bottleneck in AI applications. In-memory computing (IMC) offers an efficient solution to this problem by enabling computations within memory units, thus reducing the need for data transmission. This paper proposes a multilogic sense amplifier (MSA) with a dynamic reference voltage (DRV) generation circuit (hereafter denoted as MSA-DRV) to enhance the performance and reduce the power consumption of static random-access memory (SRAM)-based IMC. The proposed MSA-DRV performs six logic operations, namely the AND, NAND, OR, NOR, XOR, and XNOR operations, within an SRAM array by using a novel DRV circuit. The DRV circuit enables the voltage threshold to be adaptively changed according to the requirements of different operations. Experimental results indicated that the proposed MSA-DRV had lower computational latency (on average 29.9% lower) and power consumption (on average 30.6% lower) than did a conventional sense amplifier design and reconfigurable assist sense amplifier. Thus, the proposed design can overcome the von Neumann bottleneck to facilitate high-speed, energy-efficient data processing, which is crucial for AI-based and other data-intensive applications.