Design and Performance Evaluation of RISC-V Embedded Processor Using HDL

Today's world has seen the dawn of a new era with a sudden spike of interest much towards generative AI and Machine Learning throughout the globe and with computational powers beginning to show their might, we need fast and efficient microprocessors. To achieve higher efficiency, modern processors often adopt the RISC (Reduced Instruction Set Computer) design principle, which emphasizes a smaller and simpler set of instructions, each executive in a uniform amount of time. In this research, we have tried to deploy a 5-stage pipelined general-purpose microprocessor architecture that achieves a clock period of 0.59 nanoseconds, translating to an operational frequency of 1.69 GHz through the implementation of optimization techniques in Verilog code. Additionally, the use of True Single- Phase Clocking (TSPC) flip-flops reduce the transistor count per flip-flop by approximately 50%, leading to a 20% decrease in overall power consumption. This paper highlights the application of RISC-V embedded processor design in obtaining a n-stage pipelined architecture for a general-purpose microprocessor using Verilog HDL on ModelSim and Xilinx.