Soft-Aided Error-and-Erasure Decoding of BCH-SPC Product Codes with Bit Marking

In this paper, we propose a novel soft-aided error-and-erasure decoding method for product codes with Bose-Chaudhuri-Hocquenghem (BCH) and single parity check (SPC) component codes based on bit marking. We mark all the reliable bits in the decoding of BCH component codes according to scaled reliability to reduce miscorrection, and we only flip the unreliable bits in the decoding of SPC component codes. A backtrack scheme is introduced to further improve the performance. The complexity of our proposed decoder is much lower than those of conventional soft-aided iterative decoders as the reliability of each bit remains unchanged when decoding, and only ternary message is exchanged between the component decoders. Simulations show that the proposed decoding method outperforms previous decoder by 0.1 dB, and the computational complexity is reduced by about 60% compared with 5G-LDPC codes at the cost of about 0.5dB performance loss.

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Publication Details

Published
2024-12-13
DOI
https://doi.org/10.1109/iccc62609.2024.10942076
Primary Topic
VLSI and Analog Circuit Testing
Type
article
Field-Weighted Citation Impact
0.00

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article

Soft-Aided Error-and-Erasure Decoding of BCH-SPC Product Codes with Bit Marking

Yangmin Li, Ming Jiang, Qiang Wang
VLSI and Analog Circuit Testing
article

Soft-Aided Error-and-Erasure Decoding of BCH-SPC Product Codes with Bit Marking

Yangmin Li, Ming Jiang, Qiang Wang
article en

Abstract

In this paper, we propose a novel soft-aided error-and-erasure decoding method for product codes with Bose-Chaudhuri-Hocquenghem (BCH) and single parity check (SPC) component codes based on bit marking. We mark all the reliable bits in the decoding of BCH component codes according to scaled reliability to reduce miscorrection, and we only flip the unreliable bits in the decoding of SPC component codes. A backtrack scheme is introduced to further improve the performance. The complexity of our proposed decoder is much lower than those of conventional soft-aided iterative decoders as the reliability of each bit remains unchanged when decoding, and only ternary message is exchanged between the component decoders. Simulations show that the proposed decoding method outperforms previous decoder by 0.1 dB, and the computational complexity is reduced by about 60% compared with 5G-LDPC codes at the cost of about 0.5dB performance loss.

Southeast University (CN)
National Natural Science Foundation of China
Openalex Percentile: Top 68%
VLSI and Analog Circuit Testing
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Soft-Aided Error-and-Erasure Decoding of BCH-SPC Product Codes with Bit Marking — Yangmin Li, Ming Jiang, et al. · (2024) | TGRS Research Map | TGRS