Improved DOG Algorithm for Edge Enhancement of Images on ASICs

Edge enhancement techniques prominently accentuate object information in images, which is crucial for tasks such as target detection, image segmentation, and object recognition. Currently, despite various advancements in edge enhancement algorithms, challenges remain in terms of resource consumption, computational complexity, as well as algorithm's generality and flexibility. To address these challenges, this paper proposes a hardware-implemented edge enhancement algorithm based on the Difference of Gaussian (DOG) operator for high-frequency component extraction. It introduces modules for salt-and-pepper noise removal, ringing artifact suppression, and overshoot compensation to mitigate DOG limitations. The flexibility of the algorithm is enhanced through local statistical adjustments of detection results. In hardware design leveraging ASIC technology, a parallel pipelined computing architecture is crafted tailored to the characteristics of edge detection operators, while adopting fixed-point quantization and other techniques to expedite computational performance. This design, utilizing 12nm standard CMOS technology, attains a total power consumption of 28.554mw and a total area of 59338µm2. It processes a VGA-standard image (640x480) in 0.663ms at 500MHz, and achieves a maximum frame rate of 60fps for 4K images (2592×1944), outperforming recent studies in terms of speed. Furthermore, the designed hardware circuit was validated using universal verification methodology (UVM), confirming that the functionality and timing are in line with expectations.