Performance Comparison Between HLS and HDL on Load Design of VTA Accelerator

The increasing complexity of DNN networks makes it harder to quickly design and deploy complete DNN accelerators in FPGA platforms. High-level-synthesis (HLS) is a common solution to simplify the design process and increase the abstraction level in system development. However, whether HLS compilation could make full use of hardware and timing resources is always needed to be considered. In this paper, a comparative study of HLS and HDL are presented focusing on load design of Versatile Tensor Accelerator (VTA). The design method of two development tools are introduced in detail. Through fine-grained instruction analysis, it can be determined that the AXI bus mechanism of HDL version is superior to HLS. Based on Xilinx ZCU104 development board, YOLOV3 are deployed and network performance evaluations are proposed. The results show that HDL design can greatly improve the load bandwidth compared with HLS, the resource utilization and power consumption are also better than HLS, which indicates limitations of HLS design in load data optimization.