VLSI Parasitic Capacitance Extraction Based on Pattern Matching Using Modified Machine Learning Methods

The increasing complexity in the process of IC design and verification has made the rule-based methods widely used by layout parasitic extraction (LPE) tools meet more and more challenges in precision, due to the increasingly severe parasitic effects resulting from the rapid growth in chip integration especially for Very Large-Scale Integration (VLSI). Based on the machine learning algorithms, a new pattern segmentation and combination method is proposed and a corresponding pattern library is established, which is more suitable for the two automatic classification models developed in this research. Two kinds of machine learning networks are trained for experiments and comparisons. For the CNN model, the number of network parameters at different depths and the effect of training layer depth on classification accuracy are compared. For the KNN algorithm, fuzzy distance pre-processing is performed on samples, and a KD-Tree model is established to store and retrieve the “distance” of point pairs. The classification accuracy of models on different training datasets is analyzed. For the labeled pattern datasets, the KNN classification model achieved a better result; Performance improvement is required only in certain mirror patterns. For a set of patterns that are not explicitly classified, the model can potentially be adapted into an unsupervised method to assist in building a pattern library. This method possesses the potential benefit of simplifying the introduction of new processes, preventing the occurrence of pattern mismatch, and saving costs when the computing resource is limited.