Unveiling the impact of trap defects on the structural-electrical correlation in dual-layer dielectrics of 4H-SiC-based MOS capacitors

This study presents a comprehensive analysis of Al/Eu₂O₃/SiO₂/4H-SiC MOS capacitors, utilizing a dual gate dielectric stack of Eu₂O₃ and SiO₂ on 4H-SiC to specify correlation between device parameters. Transition in film structure with heat treatment, with optimal crystallization and minimized stress at 800 ° C has verified by X-ray diffraction and atomic force microscopy . Silicate-containing bonds were observed during surface chemical characterization at elevated temperatures. Electrical measurements indicate that annealing at moderate temperatures improves capacitance stability and lowers interface state density, resulting in flat band voltage adjustment. The device characteristics were significantly influenced by series resistance. The incorporation of thermally grown SiO₂ was observed to enhance the electrical properties of the devices at higher annealing temperatures by reducing interface defect sites . A notable degradation in barrier height was observed, likely due to carbon immigration and parasitic silicate formation occurring at temperatures exceeding 600 °C. This research demonstrates a promising electrical configuration on 4H-SiC that balances crystallinity and defect control, paving the way for advanced MOS devices suitable potential future applications. • Optimized dual-layer Eu₂O₃/SiO₂ improves trap density on 4H-SiC MOS capacitors. • Structural integrity correlates with enhanced surface chemistry and device reliability. • FTIR, Raman and AFM reveal electrochemistry and morphology transformations. • Thermal treatment impacts trap distribution, reducing electrical losses. • Capacitance studies link surface traps with enhanced barrier height variations.