Design and Implementation of a RISC-V Vector Processor for Convolutional Neural Networks

To address the computational performance requirements of IoT platforms when deploying Convolutional Neural Network (CNN) models, this paper designs a scalar main processor and vector coprocessor combination architecture based on the RISC-V architecture. The processor implements the RISC-V basic integer instruction set, integer multiply-divide instruction set, CSR instructions, and vector instruction set. To verify the functionality of the hardware design, simulation tests and FPGA board-level verification were conducted to successfully test the processor's instruction functions, and its performance was evaluated by Coremark benchmark tests. The test results show that the introduction of the vector coprocessor significantly improves the performance of the scalar main processor when performing CNN tasks. Using vector instructions compared to scalar instructions, the average acceleration ratio reaches 5.135, demonstrating powerful computational acceleration especially in multi-parallel computing tasks, providing an efficient solution for AI and edge computing applications.