High‐speed and reduced energy delay product TCAM on FPGA for network routers

Abstract Ternary content‐addressable memory (TCAM) is widely used in the design of high‐speed search engines such as network routers and artificial‐intelligence‐based applications. However, traditional TCAM designs suffer from two major drawbacks. Static random access memory (RAM)‐based TCAMs do one operation at a time, causing the search operation to be suspended while the update operation is in progress, rendering them unsuitable for applications with high‐frequency updates. Moreover, during the implementation of wider TCAMs, when the match results are transferred from one slice to another, the last look‐up table (LUT) in the slice is always set to logic one, which results in resource wastages. This research aims to overcome the problems associated with traditional TCAM design. The proposed work used six‐input (RAM64X1S) LUTs in field‐programmable gate arrays by allowing both search and update operations to be performed simultaneously during the data update in a particular LUT. To overcome resource wastage, the proposed design used four RAM64X1S blocks instead of RAM64M blocks. Moreover, the proposed TCAM architecture was considerably simpler, comprising LUTs with AND slicing, thus reducing FPGA resources such as slice registers and slice logic. For TCAM sizes of 512 × 36 and 1024 × 144, the slice utilization was reduced by 17% and 29%, respectively, with their speed being increased by 17% and 26%, respectively. Moreover, the lookup rate and the update rate of the designed TCAMs also improved considerably. The proposed architecture employed high‐speed single‐cycle searches, making it ideal for fast search applications.