Design of area and power-competent FFT architectures with radix-4 butterfly structures

In the field of signal processing, systematic examination of the frequency components of a real-time signal is often a top priority. In digital signal processing, the Fast Fourier Transform (FFT) computes the Fourier Transform quickly and accurately, which is significant for finding out and studying frequency components. It develops the performance of radio frequency signals in electronic circuits. For the FFT calculations, the very noteworthy structure is called a butterfly as it is an operation over a complex number. This calculation involves addition and multiplication operations of input real-time signals with applicable coefficients. Therefore, the accurate and optimized design of these butterfly units can result in FFT architectures with decreased area and power consumption. In this paper, two different 16-point FFT structures with radix-4 butterfly units for both DIT as well as DIF are designed. The main goal of this design is to reduce the number of butterflies i.e. addition and multiplication arithmetic operators, so that the designed FFT structures is area and power competent. The area and power-competent FFT architectures are designed using high-level transformation techniques like folding and retiming. Folding is a transformation technique that reduces the silicon area of VLSI hardware implementation by time multiplexing all arithmetic units of a DSP system to a single unit. Retiming is a transformation technique that increases any DSP system's functioning speed by increasing operating frequency. The FFT structures in this paper are designed using Verilog hardware language and implemented on the ML605 Virtex-6 FPGA board. The paper compares the number of butterflies, FPGA resources, and power consumption of two structures for real-time signal DIT and DIF FFT algorithms.