Fluorine-Treated Top-Gate InAlZnO TFT for 2T0C DRAM With Long Data Retention at <i>V</i> _hold = 0 V

Top-gate InAlZnO (IAZO) thin-film transistors (TFTs) fabricated with plasma-enhanced atomic layer deposition (PEALD) are investigated for 2T0C DRAM cells. By using Ar plasma to treat the source/drain (S/D) region, significant improvement in S/D contact properties is obtained and the on-state current (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}\text {)}$ </tex-math></inline-formula> is boosted by about three orders of magnitude. Furthermore, we employ a fluorine-treated method to modulate the threshold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}\text {)}$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> of the top-gate IAZO TFT. By optimizing the fluorine-treatment parameters for the IAZO channel, the resultant TFT exhibits a positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> of 0.64 V, a small subthreshold swing (SS) of 74 mV/dec, a negligible clockwise hysteresis window of ~6 mV, an excellent uniformity (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> variation <0.2 V), and an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> increase of more than 50% as compared with the untreated device. Negative bias stability (NBS) of the F-treated IAZO TFT is significantly improved, showing a negligible <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {th}}$ </tex-math></inline-formula> shift of −0.005 V after 60 min stress at −3 MV cm−1. Moreover, 2T0C DRAM cells based on the F-treated top-gate IAZO TFTs are fabricated, demonstrating a long retention time of >1 ks at zero hold voltage (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {hold}}\text {)}$ </tex-math></inline-formula>, and an excellent endurance property over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{10}}$ </tex-math></inline-formula> cycles. Finally, the top-gate IAZO TFTs and 2T0C DRAM cells with downscaled channel length are further investigated, demonstrating an <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {on}}$ </tex-math></inline-formula> of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2~\mu $ </tex-math></inline-formula>A/<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu $ </tex-math></inline-formula>m and a retention time of 80 s at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text {hold}} = 0$ </tex-math></inline-formula> V. These results indicate that the top-gate IAZO TFTs have great potential for memory applications with extremely low static power consumption.