STDP Learning Implementation with CMOS LIF Neuron and Twin-Memristor Synapse

Neuromorphic computing is an emerging field that aims to replicate the brain’s neural structure to overcome the limitations of traditional von Neumann architecture. In this paper, we present the implementation of a Spike-Timing-Dependent Plasticity (STDP) learning system using CMOS Leaky Integrate and Fire (LIF) neurons and twin-memristor synapses. Our design targets low power consumption, high computational efficiency, and adaptability for Spiking Neural Networks (SNNs). The system was built using 65nm CMOS technology, optimizing the neuron and synapse configurations to reduce power consumption and enhance learning performance. The synaptic strength is modulated by the precise timing of spikes between the pre-and post-neurons, allowing the system to mimic biological learning through Long-Term Potentiation (LTP) and Long-Term Depression (LTD). Simulation results validate the effectiveness of our system, showing improved performance over previous implementations in terms of energy efficiency, power consumption, and spike rate, making it suitable for real-time, low-power neuromorphic applications.