Comparative Analysis of p-type Graded vs Uniform Channel Double Gate Junctionless FETs

In this research, A 2D simulation model for p-type graded channel double gate with different material JLFET using spacer with high-k-dielectric (GC-DG-DM-JLFET-SP) has been developed in Silvaco(TCAD) software. The surface potential, input characteristics, output characteristics, nonidentical short channel effects like subthreshold swing (SS), and drain-induced barrier lowering (DIBL), threshold voltage variation for different drain voltages, on/off ratio, and different analog performance parameters such as transconductance generation factor $\left(g_{m} / I_{s d}\right)$, transconductance $\left(g_{m}\right)$, drain output conductance $\left(G_{D}\right)$ and early voltage ($V_{E A}$) of p-type GC-DG-DM-JLFET-SP have been compared with those of p-type uniform channel double gate with different material junctionless field effect transistor with high-k dielectric spacer (UC-DG-DM-JLFET-SP). It can be shown that the graded channel device has an excessive on/off current ratio, lower value of DIBL and SS, higher transconductance $\left(g_{m}\right)$ (for higher drain voltage), improved $G_{D}$, enhanced TGF $\left(g_{m} / I_{s d}\right)$ and slight degradation of early voltage $\left(V_{E A}\right)$.