Efficient Implementation of Group Operations for Elliptic Curve Cryptography

Group operations determine how efficiently elliptic curve cryptography (ECC) can operate. In this study, we propose efficient and optimized point addition (PA) and point doubling (PD) algorithms and hardware architectures to enhance ECC's efficiency and security. The repetitive use of PA and PD in scalar multiplication can significantly save area and time in designing ECC protocols, especially when these operations are implemented efficiently. We present a more area-time efficient design approach that consumes only 2681 slice registers with 5.495 μs latency for PA and 2309 slice registers with 4.961 μs latency for PD. The Xilinx 14.7 design tool is used to synthesize and analyze PA and PD architectures using VHDL. The Kintex-7 FPGA ‘7k70tfbg676-1’ model is used for the overall design. This design platform consumes minimal power, 0.079W, and can withstand high thermal margins of 74.9°C and 40.4W. Our proposed design achieves a lower area-delay product, with values of 0.015 for PA and 0.011 for PD, and maximizes throughput rates. The higher values of the figure of merit, 67.87 for PA and 87.29 for PD, indicate that the proposed design is highly efficient and optimized.

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Publication Details

Published
2024-11-01
DOI
https://doi.org/10.1109/spicscon64195.2024.10940954
Citations
1
Primary Topic
Cryptography and Residue Arithmetic
Type
article
Field-Weighted Citation Impact
0.78
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Efficient Implementation of Group Operations for Elliptic Curve Cryptography

Kalyan Kumar Halder, Md. Sazedur Rahman
1 citations
Cryptography and Residue Arithmetic
0.78
article

Efficient Implementation of Group Operations for Elliptic Curve Cryptography

Kalyan Kumar Halder, Md. Sazedur Rahman
article en
1 citations

Abstract

Group operations determine how efficiently elliptic curve cryptography (ECC) can operate. In this study, we propose efficient and optimized point addition (PA) and point doubling (PD) algorithms and hardware architectures to enhance ECC's efficiency and security. The repetitive use of PA and PD in scalar multiplication can significantly save area and time in designing ECC protocols, especially when these operations are implemented efficiently. We present a more area-time efficient design approach that consumes only 2681 slice registers with 5.495 μs latency for PA and 2309 slice registers with 4.961 μs latency for PD. The Xilinx 14.7 design tool is used to synthesize and analyze PA and PD architectures using VHDL. The Kintex-7 FPGA ‘7k70tfbg676-1’ model is used for the overall design. This design platform consumes minimal power, 0.079W, and can withstand high thermal margins of 74.9°C and 40.4W. Our proposed design achieves a lower area-delay product, with values of 0.015 for PA and 0.011 for PD, and maximizes throughput rates. The higher values of the figure of merit, 67.87 for PA and 87.29 for PD, indicate that the proposed design is highly efficient and optimized.

Khulna University of Engineering and Technology (BD)
Openalex Percentile: Top 17%
Cryptography and Residue Arithmetic
0.78
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