Hardware Implementation of Area-Time Efficient Modular Multiplication over NIST Prime Fields

This research presents an efficient modular multipli-cation for elliptic curve cryptography (ECC) over NIST prime fields. The development of ECC processors that can perform modular multiplication while minimizing hardware utilization is a crucial need in cryptography and cybersecurity. The efficiency of modular multiplication is a key factor that directly impacts the overall performance of ECC processors. Achieving fast modular multiplication with low hardware usage involves optimizing the design of ECPs to balance computational speed, resource utilization, and resistance to side-channel attacks. Our proposed design aims to achieve higher performance with reduced power consumption. For performance evaluation, we synthesized our design on various FPGA platforms, including Virtex-7 and Virtex-6, using different NIST primes. The mostly used 256-bit modular multiplication device utilization is reduced greatly here, and we extend this work to higher bits, i.e., 384-bit and 521-bit NIST primes.